Title :
Image smoothing and edge detection CMOS sensor array with improved signal output range
Author :
Zeffer, Tamás ; Yeargan, Jerry
Author_Institution :
Dept. of Electr. Eng., Arkansas Univ., Budapest
Abstract :
This paper consists of design, simulation, layout, and test of a CMOS image sensor array. It is an analog nonlinear circuitry with on-board photoreceptors that acquire and process the image on a single, compact VLSI chip. Spatial image processing chips implementing resistive grid have been broadly explored. One of the main drawbacks of one group of these sensors is the large percentage of analog output signal loss due to the known low CMOS sensors sensitivity and the relative large offset of the readout amplifier caused by run-to-run and in chip process variations. In our design, we modified the pixel circuit and the read out transresistance amplifier gaining back close to fifty percent of the photo signal. The motivation of the overall chip is derived from its neurobiological counterpart. It models the first stage of retinal processing at the first synapse
Keywords :
CMOS image sensors; VLSI; analogue integrated circuits; array signal processing; circuit simulation; edge detection; integrated circuit layout; integrated circuit testing; smoothing methods; CMOS image sensor array design; CMOS image sensor array layout; CMOS image sensor array simulation; CMOS image sensor array testing; VLSI chip; analog nonlinear circuitry; edge detection CMOS sensor array; image smoothing; on-board photoreceptors; read out transresistance amplifier gaining; signal output range; CMOS image sensors; Circuit simulation; Circuit testing; Image edge detection; Image processing; Photoreceptors; Sensor arrays; Signal processing; Smoothing methods; Very large scale integration;
Conference_Titel :
Mechatronics, 2006 IEEE International Conference on
Conference_Location :
Budapest
Print_ISBN :
0-7803-9712-6
Electronic_ISBN :
0-7803-9713-4
DOI :
10.1109/ICMECH.2006.252521
