Parallel Huffman decoder with an optimized look up table option on FPGA

Compression is very important for systems with limited channel bandwidth and/or limited storage size. One of the main components in image/video compression is variable length coding (VLC). This paper discusses one of the most popular VLC technique known as Huffman coding. A real time hardware parallel Huffman decoder has been successfully designed and implemented using 50,000 gate FPGA (FLEX10K20 from Altera). The parallelism is exploited in the design to achieve the high frame rate such as in JPEG and MPEG implementation. Using a parallel technique, a codeword is guaranteed to be processed within a single clock cycle. The codeword to be processed is matched with the one stored in a look up table (LUT). A LUT is needed during the coding and decoding process. In order to save memory cost, an optimized LUT is suggested. This paper does not intend to complete an optimized operating speed design, but instead only concentrates on producing a workable real-time decoder design