Analysis and realization of a low noise amplifier with high linearity and low power dissipation

Abstract-This paper presents a low noise amplifier (LNA) with high linearity and low power performance for IEEE 802.11a. The proposed LNA uses a current reuse circuit (CRC) to reduce its power dissipation and a multiple gated circuit (MGC) to improve its linearity. The theoretical analyses of noise, linearity and gain have been described in details to demonstrate the benefits of the LNA. The circuit is fabricated with 0.18 mum CMOS process. The measurement results of the LNA show that gain of 15 dB, isolation of -25 dB, input 1 dB compression point (IPidB) of -18 dBm, input third order intercept point (IIP3) of -3.5 dBm, power dissipation of 7.2 mW and noise figure of 4.2 dB for 1.8 V supply voltage at 5.25 GHz.