A novel high-speed programmable counter architecture for 5GHz WLAN application

The design and simulation of a novel high-speed programmable counter circuit for 5GHz frequency synthesizer application in WLAN is presented. Compared with the conventional programmable counter circuit, it has a higher speed by using high-speed dual modulus prescaler (DMP) architecture that can operate as fast as asynchronous divider circuits and a new programmable counter structure. The proposed DMP circuit makes uses of the character of asynchronous circuits to increase running frequency. Based on this topology, a programmable counter is implemented in 0.18 μm TSMC standard CMOS process. Simulation result shows that a maximum operating frequency 6.3GHz is obtained at 1.8V supply voltage with a power consumption of 6.7 mW for the proposed DMP architecture and that a maximum operating frequency 4GHz is obtained at 1.8V supply voltage for the conventional DMP using the same synchronous part. Simulation result also shows that the proposed programmable counter can operate between 0.1GHz and 6.3GHz correctly.