Title :
Mixed-voltage-tolerant I/O buffer using a clamping dynamic gate bias generator
Author :
Lee, Tzung-Je ; Chang, Wei-Chih ; Wang, Chua-Chin
Author_Institution :
Nat. Sun Yat-Sen Univ., Kaohsiung
fDate :
Oct. 30 2007-Nov. 2 2007
Abstract :
A mixed-voltage-tolerant I/O buffer implemented in CMOS 2P4M 0.35 mum process is proposed in this paper. By using a clamping dynamic gate bias circuit, which possesses the ability of low-power DC bias generation using clamping transistor in feedback loop, VDDIO detection, and level shift, the proposed design can transmit and receive digital signals with voltage levels of 5/3.3/1.8 V without any gate-oxide overstress and leakage current path. The maximum transmitting speed of the proposed I/O buffer is simulated to be 142/166/100 MHz given the load of 20 pF using HSPICE for VDDIO = 5/3.3/1.8 V, respectively.
Keywords :
CMOS integrated circuits; buffer circuits; feedback; low-power electronics; transistors; CMOS; VDDIO detection; clamping dynamic gate bias circuit; clamping transistor; digital signals; feedback loop; low-power DC bias generation; mixed-voltage-tolerant I/O buffer; CMOS process; Clamps; DC generators; Feedback circuits; Feedback loop; Leak detection; Leakage current; Signal design; Signal generators; Voltage;
Conference_Titel :
TENCON 2007 - 2007 IEEE Region 10 Conference
Conference_Location :
Taipei
Print_ISBN :
978-1-4244-1272-3
Electronic_ISBN :
978-1-4244-1272-3
DOI :
10.1109/TENCON.2007.4428856
