• DocumentCode
    2751602
  • Title

    An efficient scheme to diagnose scan chains

  • Author

    Narayanan, Sridhar ; Das, Ashutosh

  • Author_Institution
    Sun Microsyst. Inc., Mountain View, CA, USA
  • fYear
    1997
  • fDate
    1-6 Nov 1997
  • Firstpage
    704
  • Lastpage
    713
  • Abstract
    The scan chain needs to operate correctly to utilize the scan features in a design. The presence of defects in the chain can invalidate the test and debug methodology for a design. In this paper we present a novel strategy to efficiently diagnose a scan chain. The main idea is to add circuitry to a scan flop to enable its scan-out port to be either set or reset. Use of this circuitry requires no additional control signals, and has no impact on the timing of the design. Based on this set/reset feature, we then present a global strategy to efficiently incorporate it in a scan design. This strategy takes into account disparities in the defect probabilities and controllability/observability attributes of flops in a scan chain. An algorithm to optimally modify a subset of the flops to maximize diagnostic resolution is described. Experimental results on two devices highlight the advantages of the proposed strategy
  • Keywords
    design for testability; flip-flops; logic testing; optimisation; probability; sequential circuits; complexity; controllability/observability; defect probabilities; defects; diagnostic resolution; disparities; dynamic programming; flop diagnosis; optimisation; scan chains; set/reset circuit; Circuit faults; Circuit testing; Controllability; Flip-flops; Logic testing; Microelectronics; Observability; Signal design; Sun; Timing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Test Conference, 1997. Proceedings., International
  • Conference_Location
    Washington, DC
  • ISSN
    1089-3539
  • Print_ISBN
    0-7803-4209-7
  • Type

    conf

  • DOI
    10.1109/TEST.1997.639683
  • Filename
    639683