• DocumentCode
    2751736
  • Title

    Fast global elimination algorithm and low-cost VLSI design for motion estimation

  • Author

    Fan, Chih-Peng ; Lin, Sheng-Wei

  • Author_Institution
    Nat. Chung Hsing Univ., Taichung
  • fYear
    2007
  • fDate
    Oct. 30 2007-Nov. 2 2007
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    In this paper, an efficient fast full search motion estimation algorithm, which is accelerated by sub-sampled preprocess, is proposed to reduce the computation costs of block matching algorithm in video compressions. The proposed fast global elimination algorithm (FGEA) can skip unnecessary search positions by the preprocessing unit. We employ the preprocessing unit to calculate the sub-sampled sum of subblock absolute difference (sub-sampled SSAD) for each candidate macro-block (MB) in the search range, where the preprocessing can select a number of probable candidate motion blocks. Then we calculate the sum of absolute difference (SAD) from these selected candidate blocks and find out the final motion vector. The proposed FGEA which uses the sub-sampled skill, reduces the computation cost of preprocessing and maintains the same compensated video quality in comparison with the previous GEA, which almost provides the same quality as the well-known full search block matching algorithm (FSBMA). Software simulation results show that the proposed fast block matching motion estimation algorithm can reduce about 38% absolute difference (AD) costs and perform average 1.64 runtime faster than the previous GEA method on the basis of the same compensated video quality with the FSBMA Through VLSI implementations, the realization of the FGEA only needs 22.1 k gate counts to achieve real-time process 30 frames/sec CIF-format video sequences.
  • Keywords
    VLSI; data compression; image matching; image sampling; motion estimation; video coding; block matching algorithm; fast global elimination algorithm; final motion vector; low-cost VLSI design; motion estimation; sub-sampled preprocess; subblock absolute difference; sum of absolute difference; video compressions; Acceleration; Algorithm design and analysis; Computational efficiency; Computational modeling; Motion estimation; Software algorithms; Software performance; Software quality; Very large scale integration; Video compression;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    TENCON 2007 - 2007 IEEE Region 10 Conference
  • Conference_Location
    Taipei
  • Print_ISBN
    978-1-4244-1272-3
  • Electronic_ISBN
    978-1-4244-1272-3
  • Type

    conf

  • DOI
    10.1109/TENCON.2007.4428873
  • Filename
    4428873