Title :
An area-efficient low-power SC integrator for very high resolution ADCS
Author :
Zare-Hoseini, H. ; Azizi, M.Y. ; Shoaei, Omid
Abstract :
In this paper, a very area-efficient low-noise low-power correlated double sampled integrator has been presented. A fully differential class AB op-amp with preamplifier is designed with gain of 85dB, bandwidth of 12 Mrad/s and overall input referred noise floor of -171 dB. For attenuating the integrator´s op-amp thermal noise, the input transconductance is kept as large as needed and also the bandwidth of the op-amp is decreased as much as possible without the need for large compensation capacitors as in the ordinary topologies are used. The integrator is used in the front-end of a 24 bit, fourth-order single-loop Delta-Sigma modulator for a bandwidth of 1000 Rad/s. The integrator power consumption is only 2.8 mW with a single 3.0V supply in 0.6-μm CMOS technology.
Keywords :
CMOS analogue integrated circuits; differential amplifiers; integrated circuit design; integrating circuits; low-power electronics; operational amplifiers; preamplifiers; sigma-delta modulation; 0.6 micron; 2.8 mW; 24 bits; 3 V; 85 dB; CMOS technology; compensation capacitors; correlated double sampled integrator; delta-sigma modulator; differential class AB op-amp; high resolution ADC; input transconductance; low-power SC integrator; thermal noise;
Conference_Titel :
Signals, Circuits and Systems, 2003. SCS 2003. International Symposium on
Print_ISBN :
0-7803-7979-9
DOI :
10.1109/SCS.2003.1227065
