Seeds optimization algorithm of SIC test sequences in low power BIST

Single input change (SIC) test sequence has been investigated in recent years because it is effective to reduce the test power consumption. Deterministic built-in self-test (BIST) can achieve the high fault coverage with relatively short test application time and low test cost. In this paper, seeds selection scheme of SIC sequences based on deterministic ATPG test patterns is proposed for decreasing the test power consumption and test application time with high test fault coverage. Proper selection of SIC seeds is the key aspect to a successful low power deterministic BIST technique. Furthermore, simulated annealing algorithm is used to optimize the numbers of seeds. A simple hardware structure can implement the generation of SIC sequences. Experimental results based on ISCAS´85 benchmark circuits demonstrate that the proposed algorithm can reduce the number of SIC seeds. Test application time and average power can be decreased, and test fault coverage also keep high compared to random SIC (RSIC) test sequences.