Title :
Low redundancy overhead multibit error correction in memory
Author :
Zhu, Ming ; Xiao, Liyi ; Sun, Zheng ; Zhang, Yanjing ; Jiang, Yuqian ; Li, Shuhao
Author_Institution :
Microelectron. Center, Harbin Inst. of Technol., Harbin, China
fDate :
July 28 2010-Aug. 1 2010
Abstract :
As technology scales, memories have become more susceptible to radiation induced multiple bit upsets (MBUs). Multibit error correction codes (MECC) are an effective approach to mitigate MBUs in memories. This paper proposes a new codeword structure to protect memory against MBUs. Euclidean Geometry Low Density Parity Check (EG-LDPC) codes and Hamming codes are combined in the proposed codeword to assure the reliability of memory with low redundancy overhead. Furthermore, the proposed codeword can protect some longer data which is difficult for other MECCs to deal with. By using the proposed codeword, both low redundancy overhead scheme and long data width scheme for multibit error correction are presented. Finally, the proposed schemes have been implemented in Verilog and validated through a wide set of simulations. The experiment results reveal that the proposed method has a superior protection level. Compared with general MECC, it has lower redundancy and performance overheads.
Keywords :
Hamming codes; error correction codes; integrated memory circuits; redundancy; Euclidean geometry low density parity check codes; Hamming codes; Verilog; codeword structure; long data width scheme; low redundancy overhead multibit error correction; memory reliability; multibit error correction codes; multiple bit upsets; Computer architecture; Decoding; Error correction codes; Layout; Parity check codes; Redundancy; Memory; Multibit Error Correction Codes; Multiple Bit Upsets;
Conference_Titel :
Laser Physics and Laser Technologies (RCSLPLT) and 2010 Academic Symposium on Optoelectronics Technology (ASOT), 2010 10th Russian-Chinese Symposium on
Conference_Location :
Harbin
Print_ISBN :
978-1-4244-5511-9
DOI :
10.1109/RCSLPLT.2010.5615316