An efficient systolic array algorithm for the VLSI implementation of the odd-squared generalized discrete Hartley transform

An efficient design approach for a systolic array VLSI implementation of a prime-length odd-squared generalized discrete Hartley transform is presented. It uses an appropriate hardware algorithm based on an efficient decomposition of the odd-squared GDHT into two circular correlation structures having the same form and length that can be computed in parallel. Using an appropriate hardware sharing technique results in high computing speed with low hardware complexity, together with all the other advantages of the systolic array implementation of circular correlation structures as low I/O cost, regular and modular structures and local connections.