• DocumentCode
    2752160
  • Title

    Sequential test generation with advanced illegal state search

  • Author

    Konijnenburg, M.H. ; Van der Linden, J. Th ; van de Goor, A.J.

  • Author_Institution
    Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands
  • fYear
    1997
  • fDate
    1-6 Nov 1997
  • Firstpage
    733
  • Lastpage
    742
  • Abstract
    TPG for synchronous sequential circuits has received wide attention over the last two decades, yet unlike for (full-scan) combinational circuits, for many sequential benchmark circuits 100% fault efficiency still cannot be reached. This illustrates the complexity of sequential circuit ATPG. The huge search space, which exists during sequential circuit TPG, is the main reason for this complexity. Powerful techniques and heuristics are required to cope with this search space. One way to reduce the search space is the detection of illegal states. These states cannot be justified with an initialization sequence. In this paper, we propose new techniques to find illegal states and to remove the over-specification of these states by searching common fractions in the list of illegal states. Experimental results demonstrate the importance of an as complete as possible illegal state list: Higher fault efficiencies are reached for the sequential ISCAS´89 circuits (1989) and industrial circuits, together with a large reduction of CPU time
  • Keywords
    automatic testing; computational complexity; logic testing; sequential circuits; CPU time; TPG; advanced illegal state search; common fractions; complexity; fault efficiency; full-scan combinational circuits; heuristics; illegal states; industrial circuits; initialization sequence; over-specification; search space; sequential ISCAS´89 circuits; sequential benchmark circuits; sequential test generation; synchronous sequential circuits; Circuit faults; Circuit testing; Combinational circuits; Electrical fault detection; Fault detection; Integrated circuit testing; Performance evaluation; Sequential analysis; Sequential circuits; Space technology;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Test Conference, 1997. Proceedings., International
  • Conference_Location
    Washington, DC
  • ISSN
    1089-3539
  • Print_ISBN
    0-7803-4209-7
  • Type

    conf

  • DOI
    10.1109/TEST.1997.639686
  • Filename
    639686