Title :
Efficient built-in self-test algorithm for memory
Author :
Wang, Sying-Jyan ; Wei, Chen-Jung
Author_Institution :
Inst. of Comput. Sci., Nat. Chung-Hsing Univ., Taichung, Taiwan
Abstract :
We present a new pseudorandom testing algorithm for the Built-In Self-Test (BIST) of DRAM. In this algorithm, test patterns are complemented to generate state-transitions that are needed for the detection of coupling faults. As a result, the number of test patterns required is less than half of the traditional method, while the extra hardware is negligible
Keywords :
DRAM chips; built-in self test; BIST; DRAM; built-in self-test algorithm; coupling faults; pseudorandom testing; test patterns; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Computer science; Fault detection; Hardware; Logic; Random access memory; Test pattern generators;
Conference_Titel :
Test Symposium, 2000. (ATS 2000). Proceedings of the Ninth Asian
Conference_Location :
Taipei
Print_ISBN :
0-7695-0887-1
DOI :
10.1109/ATS.2000.893604
