Title :
Top-down-based timing-driven steiner tree construction with wire sizing and buffer insertion
Author :
Yan, Jin-Tai ; Huang, Shi-Qin ; Chen, Zhi-Wei
Author_Institution :
Chung-Hua Univ. Hsinchu, Hsinchu
fDate :
Oct. 30 2007-Nov. 2 2007
Abstract :
Given a set of connecting nodes in a signal net, based on the concept of sharing-buffer insertion and hidden Steiner- point assignment and the result of optimal wire width and buffer insertion in a wire segment (J.T. Yan, 2006) a top-down-based merging approach is proposed to construct a timing-driven rectilinear Steiner tree with wire sizing and buffer insertion The experimental results show that our proposed merging approach without wire sizing and buffer insertion reduces 5%~39% timing delay than the MVERT approach[5] in reasonable CPU time. Besides that, the proposed approach with wire sizing and buffer insertion reduces 28%~76% timing delay than that without wire sizing and buffer insertion for the tested signal nets.
Keywords :
buffer storage; telecommunication network routing; trees (mathematics); Steiner-point assignment; buffer insertion; optimal wire width; timing-driven rectilinear Steiner tree; top-down-based timing-driven Steiner tree construction; wire sizing; Capacitance; Circuits; Delay effects; Joining processes; Merging; Routing; Signal design; Testing; Timing; Wire;
Conference_Titel :
TENCON 2007 - 2007 IEEE Region 10 Conference
Conference_Location :
Taipei
Print_ISBN :
978-1-4244-1272-3
Electronic_ISBN :
978-1-4244-1272-3
DOI :
10.1109/TENCON.2007.4428902