Mapping physical defects to logic level for defect oriented testing

A uniform fault model for representing physical defects in components of digital circuits is introduced. Physical defects are modeled as parameters in generic Boolean differential equations. Solutions of the equations give the conditions at which defects are locally activated. The defect activation conditions are used as functional fault models on the logic level for fault simulation purposes. The functional fault model can be regarded also as an interface for mapping faults from one system level to another, helping to carry out hierarchical test generation or hierarchical fault simulation in digital systems. Experiments have shown the feasibility and efficiency of the method compared to the classical stuck-at fault based approaches.