DocumentCode
2752521
Title
Spirit: satisfiability problem implementation for redundancy identification and test generation
Author
Gizdarski, Emil ; Fujiwara, Hideo
Author_Institution
Dept. of Comput. Syst., Rousse Univ., Rousse, Bulgaria
fYear
2000
fDate
2000
Firstpage
171
Lastpage
178
Abstract
In this paper an efficient test pattern generation (TPG) algorithm for combinational circuits based on the Boolean satisfiability method (SAT) is presented. We examine some not so popular approaches as a single cone processing, single path oriented propagation and backward justification. We give a new definition for SAT-based test generation and present duality of learning phenomenon. The resultant ATPG system, called SPIRIT, combines the flexibility of SAT-based TPG algorithms with the efficiency of structural TPG algorithms. Experimental results demonstrate the efficiency and robustness of the proposed TPG algorithm. Without fault simulation, SPIRIT is able to generate complete test sets for the ISCAS´85 benchmark circuits and full scan version of the ISCAS´89 benchmark circuits within 3 minutes on a 450 MHz Pentium-III PC
Keywords
automatic test pattern generation; combinational circuits; computability; logic testing; ATPG system; Boolean satisfiability method; SPIRIT; combinational circuits; test pattern generation; test sets; Automatic test pattern generation; Circuit faults; Circuit simulation; Circuit testing; Combinational circuits; Electronic mail; Redundancy; Robustness; System testing; Test pattern generators;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Symposium, 2000. (ATS 2000). Proceedings of the Ninth Asian
Conference_Location
Taipei
ISSN
1081-7735
Print_ISBN
0-7695-0887-1
Type
conf
DOI
10.1109/ATS.2000.893621
Filename
893621
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