DocumentCode
2752643
Title
A BIST methodology for at-speed testing of data communications transceivers
Author
Lin, S.L. ; Mourad, S. ; Krishnan, S.
Author_Institution
Intelligent Micro Inc., San Jose, CA, USA
fYear
2000
fDate
2000
Firstpage
216
Lastpage
221
Abstract
This paper discusses a new BIST methodology suitable for functional testing of transceivers on a data communications chip. Practical circuits are presented which allow the at-speed resting of various functional blocks. The concept has been applied to test a 400 Mbps 3-port IEEE 1394a system. The silicon for the 0.35 μm CMOS implementation is expected in early 2001
Keywords
CMOS integrated circuits; automatic testing; built-in self test; data communication equipment; integrated circuit testing; telecommunication equipment testing; transceivers; 0.35 micron; 3-port IEEE 1394a system; 400 Mbit/s; BIST methodology; CMOS implementation; at-speed testing; data communications chip; data communications transceivers; functional testing; Added delay; Built-in self-test; Circuit testing; Data communication; Decoding; Delay systems; Jitter; Logic testing; Performance evaluation; Transceivers;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Symposium, 2000. (ATS 2000). Proceedings of the Ninth Asian
Conference_Location
Taipei
ISSN
1081-7735
Print_ISBN
0-7695-0887-1
Type
conf
DOI
10.1109/ATS.2000.893628
Filename
893628
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