A hierarchical test control architecture for core based design

Author

Lee, Kuen-Jong ; Huang, Cheng-I

Author_Institution

Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan

fYear

2000

fDate

2000

Firstpage

248

Lastpage

253

Abstract

Recently system-on-chip (SOC) design based on IP cores has become the trend of IC design. To prevent the testing problem from becoming the bottleneck of the core-based design, the IEEE P1500 Working Group is defining a test standard that can greatly simplify the core test problem. In this paper, we propose a new core-based test architecture that can support the IEEE P1500 cores as well as the well-accepted IEEE 1149.1 cores. Both the serial and parallel testing capabilities are provided. Moreover, a new hierarchical test control mechanism has been developed that facilitates the hierarchical test access for deeply embedded cores

Keywords

IEEE standards; application specific integrated circuits; automatic testing; design for testability; integrated circuit testing; IEEE 1149.1 cores; IEEE P1500 Working Group; SOC design; core based design; deeply embedded cores; hierarchical test access; hierarchical test control architecture; hierarchical test control mechanism; parallel testing capabilities; test architecture; test standard; Circuit testing; Costs; Design for testability; Design methodology; Energy consumption; Integrated circuit testing; Manufacturing; Pins; System testing; System-on-a-chip;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Symposium, 2000. (ATS 2000). Proceedings of the Ninth Asian

Conference_Location

Taipei

ISSN

1081-7735

Print_ISBN

0-7695-0887-1

Type

conf

DOI

10.1109/ATS.2000.893633

Filename

893633