Title :
A realistic fault model for flash memories
Author :
Horng, Yea-Ling ; Huang, Jing-Reng ; Chang, Tsin-Yuan
Author_Institution :
Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
Abstract :
To explore all faulty behavior on NAND-type flash memory is impractical, and the defects in the SPICE model level are considered. In this paper, two SPICE models of the flash cell are developed and used for circuit-level faulty behavior simulation. The faulty behaviors can be classified to six types and applied for the fault modeling or testing of NAND-type flash memory
Keywords :
NAND circuits; SPICE; circuit analysis computing; fault simulation; flash memories; integrated memory circuits; NAND-type flash memory; SPICE models; circuit-level faulty behavior simulation; fault model; fault modeling; faulty behavior classification; flash cell models; flash memories; testing; Capacitance; Circuit faults; Circuit simulation; Flash memory; Medical simulation; Nonvolatile memory; Random access memory; SPICE; Switches; Wires;
Conference_Titel :
Test Symposium, 2000. (ATS 2000). Proceedings of the Ninth Asian
Conference_Location :
Taipei
Print_ISBN :
0-7695-0887-1
DOI :
10.1109/ATS.2000.893637
