Control flow checking in pipelined RISC microprocessors: the Motorola MC88100 case study

The implementation of control flow checking for RISC (reduced-instruction-set computer) machines is considered. An effort is made to show and solve the problems due to the RISC features of the MC88100. Most of these features, such as pipelined execution and the delayed branching technique, make the signature consistency difficult to ensure. The desirable signal analyzer operations are formalized according to the pipeline, the delayed branching technique, and the exception handling characteristics. A practical signature analyzer architecture convenient for the MC88100 is proposed. Since the proposed formalism is very flexible, it may be used for other microprocessors. As all the signals needed by the signature analyzer are related to the processor instruction bus, an original implementation of this analyzer in the processor instruction cache memory is proposed. In order to give a realistic value of the chip area and the complexity overheads, a practical implementation using the VLSI Technology Inc. tools is presented