Title :
An analysis of a reconfigurable binary tree architecture based on multiple-level redundancy
Author :
Chen, Yung- Yuan ; Upadhyaya, Shambhu J.
Author_Institution :
Dept. of Electr. & Comput. Eng., State Univ. of New York, Buffalo, NY, USA
Abstract :
The analysis of a multiple-level redundant tree (MLRT) structure is presented for the design of a reconfigurable tree architecture. The MLRT scheme tolerates the catastrophic failure of several locally redundant modules in the corresponding locally redundant modular tree (LRMT) structure. This analysis and experimental study establishes the advantages of the MLRT structure over the LRMT structure. The switch failures are taken into account for an accurate analysis of the reliability. A new measure, called the marginal-switch-to-processing-element-area ratio (MSR), is introduced to characterize the effect of switch complexity on the reliability of the redundant system. It can be used as an evaluation criterion in the design of practical fault-tolerant multiprocessor architectures. A technique for obtaining the best spare distribution in the MLRT structure is presented.<>
Keywords :
computer architecture; fault tolerant computing; multiprocessing systems; catastrophic failure; fault-tolerant multiprocessor architectures; locally redundant modular tree; locally redundant modules; marginal-switch-to-processing-element-area ratio; multiple-level redundancy; multiple-level redundant tree; reconfigurable binary tree architecture; switch failures; Area measurement; Binary trees; Computer architecture; Fault tolerance; Fault tolerant systems; Redundancy; Reliability; Switches; Topology; Very large scale integration;
Conference_Titel :
Fault-Tolerant Computing, 1990. FTCS-20. Digest of Papers., 20th International Symposium
Conference_Location :
Newcastle Upon Tyne, UK
Print_ISBN :
0-8186-2051-X
DOI :
10.1109/FTCS.1990.89366