VLSI design of high-throughput processing element for real-time particle filtering

This paper presents a VLSI ASIC design of a high-throughput processing element for real-time particle filtering applications. The implementation is based on robust and efficient fixed-point processing algorithms. The high-throughput is achieved through two-level pipelining and preserving the inherent parallelism. The pipeline depth is balanced among sub-units to reduce clock loading via reduction of unnecessary registers. The processing element can be used as a standalone particle filter or a part of parallel particle filters for high-speed and/or larger particles.