Title :
Charge sharing fault analysis and testing for CMOS domino logic circuits
Author :
Cheng, Ching-Hwa ; Jone, Wen-Ben ; Wang, Jim-Shyan ; Chang, Shih-Chieh
Author_Institution :
Dept. of Comput. Sci. & Inf. Eng., Nat. Chung Cheng Univ., Chiayi, Taiwan
Abstract :
Because domino logic design offers smaller area and faster delay than conventional CMOS design, it is very popular in the high-performance processor. However, domino logic suffers from several problems and one of the most notable ones is the charge sharing problem. In this paper, we describe a method to measure the sensitivity of the charge-sharing problem for each domino gate. In addition, our algorithm also generates test vectors to detect the worst case of charge-sharing fault
Keywords :
CMOS logic circuits; automatic testing; delays; fault diagnosis; logic gates; logic testing; CMOS domino logic circuits; charge sharing fault analysis; delay; domino gate; domino logic design; sensitivity measurement; test vectors; CMOS logic circuits; CMOS process; Capacitance; Circuit faults; Circuit testing; Clocks; Fault detection; Logic circuits; Logic design; Logic testing;
Conference_Titel :
Test Symposium, 2000. (ATS 2000). Proceedings of the Ninth Asian
Conference_Location :
Taipei
Print_ISBN :
0-7695-0887-1
DOI :
10.1109/ATS.2000.893663
