Title :
Testing domino circuits in SOI technology
Author :
MacDonald, Eric ; Touba, Nur A.
Author_Institution :
Adv. PowerPC Dev., IBM Corp., Austin, TX, USA
Abstract :
The proliferation of both partially depleted silicon-on-insulator (PDSOI) technology and domino circuit styles has allowed for increases in circuit performance beyond that of scaling traditional bulk CMOS static circuits. However, interactions between dynamic circuit styles and PD-SOI complicate testing. This paper describes the issues of testing domino circuits fabricated in SOI technology and new tests are proposed to address the interactions. A fault modeling analysis is described which demonstrates that the overall fault coverage can be improved beyond that of traditional testing of domino circuits in bulk technology
Keywords :
CMOS logic circuits; automatic testing; fault simulation; integrated circuit testing; leakage currents; logic testing; silicon-on-insulator; CMOS logic; SOI technology; domino circuits; dynamic circuit styles; fault modeling analysis; overall fault coverage; parasitic bipolar leakage; CMOS technology; Capacitance; Circuit faults; Circuit testing; Delay; Leak detection; Logic arrays; Logic circuits; Silicon on insulator technology; Vehicle dynamics;
Conference_Titel :
Test Symposium, 2000. (ATS 2000). Proceedings of the Ninth Asian
Conference_Location :
Taipei
Print_ISBN :
0-7695-0887-1
DOI :
10.1109/ATS.2000.893664
