Title : 
Noise performance of single-electron depressing synapses for neuronal synchrony detection
         
        
            Author : 
Oya, Takahide ; Asai, Tetsuya ; Kagaya, Ryo ; Amemiya, Yoshihito
         
        
            Author_Institution : 
Graduate Sch. of Inf. Sci. & Technol., Hokkaido Univ., Sapporo, Japan
         
        
        
        
            fDate : 
31 July-4 Aug. 2005
         
        
        
            Abstract : 
Synchrony detection between burst and non-burst spikes is known to be one functional example of depressing synapses. Kanazawa et al. demonstrated synchrony detection with MOS depressing synapse circuits. They found that the performance of a network with depressing synapses that discriminates between burst and random input spikes increases nonmonotonically as the static device mismatch is increased. We designed a single-electron depressing synapse and constructed the same network as in Kanazawa´s study to develop noise-tolerant single-electron circuits. We examined the temperature characteristics and explored possible architecture that enables single electron circuits to operate at T > 0 K.
         
        
            Keywords : 
MOS integrated circuits; MOS logic circuits; burst noise; logic design; neural nets; synchronisation; MOS depressing synapse circuit; neuronal synchrony detection; noise-tolerance; single-electron circuit; single-electron depressing synapse; Circuit noise; Computer architecture; Electrons; Hopfield neural networks; Neurons; Noise robustness; Quantum computing; Semiconductor device noise; Temperature; Tunneling;
         
        
        
        
            Conference_Titel : 
Neural Networks, 2005. IJCNN '05. Proceedings. 2005 IEEE International Joint Conference on
         
        
            Print_ISBN : 
0-7803-9048-2
         
        
        
            DOI : 
10.1109/IJCNN.2005.1556377