Title :
A generalized interconnect model for data path synthesis
Author :
Ly, Tai A. ; Elwood, W. Lloyd ; Girczyc, Emil F.
Author_Institution :
Audesyn Inc., Edmonton, Alta., Canada
Abstract :
This multilevel interconnect model for VLSI data path synthesis is designed for synthesis under interconnect constraints. Two novel algorithms for dynamic interconnect allocation and interconnect synthesis are also described. The algorithms help implement the generalized interconnect model in the ELF hardware compiler
Keywords :
VLSI; circuit layout CAD; ELF hardware compiler; VLSI data path synthesis; dynamic interconnect allocation; interconnect constraints; interconnect synthesis; multilevel interconnect model; Circuit synthesis; Counting circuits; Delay; Hardware; Integrated circuit interconnections; Merging; Production; Reduced instruction set computing; Registers; Signal synthesis;
Conference_Titel :
Design Automation Conference, 1990. Proceedings., 27th ACM/IEEE
Conference_Location :
Orlando, FL
Print_ISBN :
0-89791-363-9
DOI :
10.1109/DAC.1990.114849
