Testability Exploration of 3-D RAMs and CAMs

Author

Huang, Yu-Jen ; Li, Jin-Fu

Author_Institution

Dept. of Electr. Eng., Nat. Central Univ., Jhongli, Taiwan

fYear

2009

fDate

23-26 Nov. 2009

Firstpage

397

Lastpage

402

Abstract

Three-dimensional (3-D) integration is an emerging integrated circuit technology. It offers many advantages over the 2-D integration. However, testing 3-D chips is a very challenging job. The testing of a 3-D chip includes the testing for known good die (KGD) and the testing of stacked 3-D chip. This paper analyzes the test complexities of 3-D random access memories (RAMs) and content addressable memories (CAMs) in the phase of testing of stacked 3-D ICs with functional faults. Analysis results show that the 3-D CAMs and RAMs can be tested with lower test complexity than the 2-D ones. Furthermore, simple design-for-testability (DFT) methods are proposed to reduce the test complexity of 3-D RAMs and CAMs further.

Keywords

content-addressable storage; design for testability; fault diagnosis; integrated circuit design; integrated circuit testing; random-access storage; 3-D CAMs; 3-D RAMs; 3-D content addressable memories; 3-D random access memories; design-for-testability methods; functional faults; known good die; test complexities; three-dimensional integration; CADCAM; Cams; Circuit testing; Computer aided manufacturing; Integrated circuit interconnections; Integrated circuit layout; Integrated circuit technology; Random access memory; Read-write memory; Three-dimensional integrated circuits; 3-D integration; CAMs; RAMs; Testability;

fLanguage

English

Publisher

ieee

Conference_Titel

Asian Test Symposium, 2009. ATS '09.

Conference_Location

Taichung

ISSN

1081-7735

Print_ISBN

978-0-7695-3864-8

Type

conf

DOI

10.1109/ATS.2009.59

Filename

5359294