A reconfigurable parallel architecture for SVM classification

The availability of powerful field programmable gate arrays (FPGA) has been exploited for their ability to rovide hardware solutions for many application areas, resulting in high-performance systems that can operate in real time by operating in parallel. The support vector machine computational paradigm can be cast as a collection of multiple streams operating in parallel on one such FPGA. This paper presents a parallel architecture that implements an SVM on a Xilinx FPGA. The results obtained by using this architecture for a complex pattern classification from high-energy physics involving thousands of patterns are reported and discussed, comparing the performance obtained by this architectural solution to that of a simpler sequential architecture.