Title :
Layout synthesis of MOS digital cells
Author_Institution :
Digital Equipment Corp., Hudson, MA, USA
Abstract :
The main issues specific to the cell generation of MOS digital circuits are reviewed. The discussion concentrates on the direct use of arbitrary cells, or the quick generation of new library items, rather than the application of general place and route algorithms. Specifically, transistor ordering for Boolean gates, routing a cell, and polygon generation are discussed
Keywords :
MOS integrated circuits; circuit layout CAD; Boolean gates; MOS digital cells; MOS digital circuits; cell generation; cell routing; layout synthesis; library items; polygon generation; transistor ordering; Assembly; CMOS technology; Circuit synthesis; Compaction; Digital circuits; Logic; MOSFETs; Read only memory; Software libraries; Solid modeling;
Conference_Titel :
Design Automation Conference, 1990. Proceedings., 27th ACM/IEEE
Conference_Location :
Orlando, FL
Print_ISBN :
0-89791-363-9
DOI :
10.1109/DAC.1990.114861
