Title :
A Jitter Characterizing BIST with Pulse-Amplifying Technique
Author :
Chao, An-Sheng ; Chang, Soon-Jyh
Author_Institution :
Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
Abstract :
A built-in self-test (BIST) circuit for jitter measurement is proposed. The BIST circuit contains an improved cyclic time-to-digital converter (TDC) to achieve 6-ps resolution, and a pulse amplifier (PA) in front of the cyclic TDC to equivalently enhance timing resolution to 0.6 ps. The quantity of jitter is derived by analyzing the digital output codes of the BIST circuit. The input frequency range of the signal-under-test (SUT) is from 200 MHz to 2 GHz for 0.6-ps timing resolution, and from 100 Hz to 2 GHz for 6-ps timing resolution. In addition to the wide input frequency range and fine resolution, the proposed BIST reduces testing time maximally by 95 % in comparison with the conventional BIST circuit based on component-invariant vernier delay line TDC. The presented BIST circuit occupies 0.6 × 0.336 mm2 in a 0.18-um CMOS process.
Keywords :
CMOS digital integrated circuits; analogue-digital conversion; built-in self test; pulse amplifiers; timing jitter; BIST circuit; CMOS process; built-in self-test circuit; component-invariant vernier delay line TDC; cyclic TDC; cyclic time-to-digital converter; digital output codes; frequency 100 Hz to 2 GHz; jitter measurement; pulse amplifier; signal-under-test; size 0.18 mum; timing resolution; Built-in self-test; CMOS process; Circuit testing; Delay lines; Frequency; Jitter; Pulse amplifiers; Pulse circuits; Signal resolution; Timing; Jitter; built-in self-test; phase locked loops; pulse amplifier;
Conference_Titel :
Asian Test Symposium, 2009. ATS '09.
Conference_Location :
Taichung
Print_ISBN :
978-0-7695-3864-8
DOI :
10.1109/ATS.2009.23
