Title :
A Partially-Exhaustive Gate Transition Fault Model
Author :
Keller, Brion ; Meehl, Dale ; Uzzaman, Anis ; Billings, Richard
Author_Institution :
Cadence Design Syst., Endicott, NY, USA
Abstract :
This paper shows a way to define a partially-exhaustive gate transition fault model for use in catching defects that escape when using more traditional fault models. We define the gate-level transitions ATPG must create for this fault model and how this may catch un-modeled defects. Future work will analyze results of applying tests generated using this fault model against a commercial chip design.
Keywords :
automatic test pattern generation; fault diagnosis; integrated circuit testing; ATPG; chip testing; defect diagnosis; gate-level transitions; partially-exhaustive gate transition fault model; Automatic test pattern generation; Circuit faults; Circuit testing; Fault detection; Fault diagnosis; Inverters; Manufacturing processes; Propagation delay; Silicon; System testing; delay defect modeling; transition delay fault model;
Conference_Titel :
Asian Test Symposium, 2009. ATS '09.
Conference_Location :
Taichung
Print_ISBN :
978-0-7695-3864-8
DOI :
10.1109/ATS.2009.62
