DocumentCode
275388
Title
Global hardware synthesis from behavioral dataflow descriptions
Author
Scheichenzuber, Josef ; Grass, Werner ; Lauther, Ulrich ; März, Sabine
Author_Institution
Siemens AG, Munich, Germany
fYear
1990
fDate
24-28 Jun 1990
Firstpage
456
Lastpage
461
Abstract
A new bottom-up logic synthesis technique for general behavioral descriptions is reported. The technique extends traditional straight-line code synthesis by allowing hierarchical, block-structured dataflow graphs with block-level parallelism. Program path probabilities are taken into account, and both high-level synthesis and design-space exploration are addressed
Keywords
logic CAD; behavioral dataflow descriptions; block-level parallelism; block-structured dataflow graphs; bottom-up logic synthesis; design-space exploration; global hardware synthesis; high-level synthesis; program path probabilities; straight-line code synthesis; Costs; Delay estimation; Digital systems; Hardware; High level synthesis; Multiplexing; Registers; Scheduling algorithm; Topology; Wiring;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 1990. Proceedings., 27th ACM/IEEE
Conference_Location
Orlando, FL
ISSN
0738-100X
Print_ISBN
0-89791-363-9
Type
conf
DOI
10.1109/DAC.1990.114899
Filename
114899
Link To Document