Silicon-hybrid wafer-scale integration achieved with multilevel aluminum interconnects

A silicon-hybrid wafer-scale integration (WSI) technique has been developed to interconnect complementary metal-oxide semiconductor (CMOS) circuits. Electrical performance tests and processing diagnostics reveal that the interconnect design is very promising. The wafer-scale integrated circuit was fabricated by mounting two CMOS integrated circuit dies into etched wells and then planarizing the surface of the silicon wafer substrate. Next the wafer´s surface was coated with a photosensitive polyimide and patterned with vias to accommodate the interconnecting conductors. The CMOS dies were two-bit shift registers and were electrically interconnected with aluminum conductors using conventional silicon processing techniques. A diagnostic evaluation was accomplished to determine the electrical continuity of the conductors and via contacts. When compared to a complementary wire-bonded interconnect scheme, the silicon WSI technology was found to be the superior performer at 1-MHz operating frequencies. Discontinuous interconnects were evaluated and the failures were identified to occur at the severe topographical steps encountered on the substrate wafer´s surface