Testing Embedded Memories in the Nano-Era: Will the Existing Approaches Survive?

With the technology scaling and increase in integration density, severe static (e.g., random dopant, subwavelength lithography, etc) and dynamic (e.g., voltage, temperature, etc) variations will rise. It is widely recognized that variability in device characteristics and its impact on the overall reliability of the system represent major challenges to scaling and integration for present and future nanotechnology generations. Moreover, the failure mechanism in the nano-era will be more dominated by transient faults (e.g., external perturbations, radiation, power fluctuations) and intermittent faults (e.g., timing faults, degradation of the component parameters) rather than permanent faults. This shift in failure mechanisms will impact the reliability in a sever way. It is becoming very hard to guarantee the reliability with today´s extensive, hence costly, traditional approaches (e.g., testing at extreme stresses, Burn-in, etc). Moreover, such approaches may reduce the lifetime of devices fabricated using nano technology nodes. As new failure mechanisms emerge, the existing test approaches may need to be changed and/or adapted to guarantee the outgoing product quality. The question is now how to deal with this shift in failure mechanisms in order to keep an acceptable product quality for embedded memories. Can the existing test approaches do the job? Do we need to rely more on stresses rather than the algorithms themselves? However, too much stress/ Burn-in may degrade the lifetime of the chip. Do we need to move more towards DFT rather than functional testing? Is programmable DFT the ideal solution? Can on-the-fly detect/repair and reconfigure be the answer? Or do we need completely new approaches?