A Non-Intrusive and Accurate Inspection Method for Segment Delay Variabilities

Diagnosis for delay defects becomes more significant as the CMOS process advances to nanometer regime. The most challenging problems of delay fault diagnosis in nanometer process come from the process variation, which results in small delay variations. Small delay variations are difficult to be diagnosed by using existing methods based on a specific fault model. This paper presents a new estimation method for gate or interconnect delays based on the maximum likelihood estimation. The proposed method outputs most probable gate/interconnect delays that matches the measured path delays under the nominal delay distribution. Unlike the previous diagnosis methods, our method does not take any assumption on defect numbers, sizes and types (models), and thus it can be used to diagnose performance bottlenecks resulted from systematic variations. The experimental results show that the average correlation achieves 0.848 between estimated (by the proposed method) and sampled segment delays (generated from process models) for ISCAS89 benchmarks. There is a substantial improvement of 0.271 over the existing method.