CMOS amplifier using chopper stabilization and sample-and-hold techniques

A low-noise CMOS amplifier operating at a low supply voltage is developed using the noise reduction technique of chopper stabilization. Unlike the conventional chopper stabilization technique that uses low pass filter to reduce the low frequency noise, the proposed amplifier uses the chopper stabilization technique and replaces the demodulator and the low pass filter with sample-and-hold circuit and adder. A simulation shows that the noise filtering performance for the chopper stabilization with sample-and-hold technique reduces the design complexity as well as the silicon area without losing the quality of noise reduction. A noise analysis shows that although the sample-and-hold degrade the signal-to-noise ratio (SNR), the degradation can be minimized by maximizing the duty cycle, minimizing the amplifier bandwidth and accurate matching of capacitance and resistance.