DocumentCode
275394
Title
Automatic incorporation of on-chip testability circuits
Author
Ito, Noriyuki
Author_Institution
Fujitsu Ltd., Kawasaki, Japan
fYear
1990
fDate
24-28 Jun 1990
Firstpage
529
Lastpage
534
Abstract
A system which automatically incorporates testability circuits into ECL chips is presented. Three types of circuits are incorporated: (1) a random access scan circuit, (2) a clock suppression circuit for delay fault testing, and (3) a pin scan-out circuit for chip I/O pin observation in board testing. Fanout destinations of each gate in the testability circuits are localized on a chip to keep the logical net length within the limit. This system was used to develop the new Fujitsu VP-2000 supercomputer
Keywords
fault location; logic circuits; logic testing; ECL chips; Fujitsu VP-2000 supercomputer; board testing; clock suppression circuit; delay fault testing; logical net length; on-chip testability circuits; pin scan-out circuit; random access scan circuit; Automatic testing; Circuit faults; Circuit testing; Clocks; Delay; Latches; Logic design; Logic testing; Performance evaluation; System testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 1990. Proceedings., 27th ACM/IEEE
Conference_Location
Orlando, FL
ISSN
0738-100X
Print_ISBN
0-89791-363-9
Type
conf
DOI
10.1109/DAC.1990.114912
Filename
114912
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