Sequential test generation at the register-transfer and logic levels

The problem of test generation for nonscan sequential VLSI circuits is addressed. A method of test generation that efficiently generates test sequences for stuck-at faults in the logic circuit by exploiting register-transfer-level (RTL) design information is presented. The problem of sequential test generation is decomposed into three subproblems of combinational test generation, fault-free justification and fault-free state differentiation. Standard combinational test generation algorithms are used to generate test vectors for stuck-at faults in a logic-level implementation. The required state corresponding to the test vector is justified using a fault-free justification step that is performed using the RTL specification. Similarly, if the effect of the fault is propagated by the test vector to the flip-flop inputs alone, the faulty state produced is differentiated from the true next state by a differentiation step that uses the RTL specification. New and efficient algorithms for fault-free state justification and differentiation on RTL descriptions that contain arithmetic as well as random logic modules are described. This approach does not require the storage of covers or a partial state transition graph (STG) and can be used to generate tests for entire chips without scan. The proposed algorithms require significantly smaller CPU times than other test generators. Tests for a Viterbi speech processor chip were generated