Analyzing a PowerPCTM 620 microprocessor silicon failure using model checking

When silicon is available, newly designed microprocessors ore tested in specially equipped hardware laboratories, where real applications can be run at hardware speeds. However, the large volumes of code being run, plus the limited access to the internal nodes of the chip, make it extraordinarily difficult to characterize the nature of any failures that occur. In this paper, we describe how the formal verification technique of temporal logic model checking was used to quickly characterize a design error exhibited during hardware testing of the PowerPC 620 microprocessor. We claim that model checking can efficiently characterize such failures when certain pre-conditions are met. We also show how the same error could have been revealed early in the design cycle, by model checking a short and simple correctness specification. We discuss the implications of this for verification methodologies over the full design cycle