CMOS current steering logic for low-power mixed-signal systems

Author

Hiok-Tiaq Ng ; Zele, R.H. ; Allstot, D.J.

Author_Institution

Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA

fYear

1994

fDate

10-12 Oct. 1994

Firstpage

14

Lastpage

15

Abstract

An analog-friendly logic family - Current Steering Logic (CSL) has been developed for high-speed, high-precision, low-power CMOS mixed-signal ICs. The constant current characteristic of CSL provides a 100X noise reduction compared to static logic. The speed of CSL can be controlled over a wide range since it is determined by the DC bias current. A 39-stage CSL ring oscillator in standard 1.2 /spl mu/m CMOS with V/sub dd/=1.1 V and I/sub bias/=12.5 /spl mu/A exhibited 1.1 ns delay and 15 fJ PDP; another design in standard 0.8 /spl mu/m CMOS with V/sub dd/=1.0 V and I/sub bias/=0.3 /spl mu/A showed 28 ns delay and 8 fJ PDP.

Keywords

CMOS logic circuits; 0.3 muA; 0.8 micron; 1 V; 1.1 V; 1.1 ns; 1.2 micron; 12.5 muA; 28 ns; CMOS current steering logic; CSL ring oscillator; constant current characteristic; high-speed IC; low-power CMOS ICs; low-power mixed-signal ICs; noise reduction; CMOS logic circuits; CMOS process; Capacitance; Circuit noise; Delay; Logic devices; Noise reduction; Ring oscillators; Switching circuits; Working environment noise;

fLanguage

English

Publisher

ieee

Conference_Titel

Low Power Electronics, 1994. Digest of Technical Papers., IEEE Symposium

Conference_Location

San Diego, CA, USA

Print_ISBN

0-7803-1953-2

Type

conf

DOI

10.1109/LPE.1994.573186

Filename

573186