• DocumentCode
    2754257
  • Title

    Auction Based Detailed Router for 3D FPGA

  • Author

    Ashokkumar, A. ; Chiplunkar, Niranjan N.

  • Author_Institution
    Comput. Sci. & Eng. Dept., N.M.A.M. Inst. of Technol., Nitte, India
  • fYear
    2009
  • fDate
    17-20 April 2009
  • Firstpage
    59
  • Lastpage
    62
  • Abstract
    To accommodate large designs, existing 2D Field Programmable Gate arrays (FPGA) may not be sufficient. In such scenarios, 3D FPGAs will be useful. Our Algorithm makes use of Auction Based Methodology to solve the detailed routing problem in case of 3D FPGAs.
  • Keywords
    commerce; field programmable gate arrays; logic design; network routing; 2D field programmable gate array; 3D FPGA; auction based detailed router; auction based methodology; routing problem; Delay; Field programmable gate arrays; Integrated circuit interconnections; Logic devices; Pins; Reconfigurable logic; Routing; Switches; Very large scale integration; Wire; 3d FPGA; auction; detailed routing; net;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Information and Financial Engineering, 2009. ICIFE 2009. International Conference on
  • Conference_Location
    Singapore
  • Print_ISBN
    978-0-7695-3606-4
  • Type

    conf

  • DOI
    10.1109/ICIFE.2009.30
  • Filename
    5189969
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2754257