Title :
Synergistic power/area optimization with transistor sizing and wire length minimization [CMOS logic]
Author :
Yamada, M. ; Kurosawa, S. ; Nojima, R. ; Kojima, N. ; Mitsuhashi, T. ; Goto, N.
Author_Institution :
Res. & Dev. Center, Toshiba Corp., Kawasaki, Japan
Abstract :
The paper proposes a method to realize low-power control-logic modules by combining transistor-size optimization and transistor layout. When applied to a circuit with 10,000 transistors, the optimizer has reduced the average transistor size to one eighth while maintaining the same delay. The power dissipation is cut to half even when wiring capacitances are dominant.
Keywords :
circuit optimisation; CMOS logic circuits; average transistor size; delay; low-power control-logic modules; power dissipation; synergistic power/area optimization; transistor layout; transistor sizing; wire length minimization; wiring capacitances; Capacitance; Circuits; Compaction; Delay effects; Delay estimation; Minimization; Optimization methods; Power dissipation; Transistors; Wire;
Conference_Titel :
Low Power Electronics, 1994. Digest of Technical Papers., IEEE Symposium
Conference_Location :
San Diego, CA, USA
Print_ISBN :
0-7803-1953-2
DOI :
10.1109/LPE.1994.573199
