Title :
CMOS technology scaling for low voltage low power applications
Author :
Zongjian Chen ; Shott, J. ; Burr, J. ; Plummer, J.D.
Author_Institution :
Dept. of Electr. Eng., Stanford Univ., CA, USA
Abstract :
This paper reports the scaling guidelines for CMOS technologies optimized for supply voltages lower than standard values in low power applications. The optimum device structures for several lithographic generations targeted for common supply voltages are provided, using an analytical simulator/optimizer incorporating appropriate physically based models. It is shown that lowering the power consumption without significant performance loss is possible. The advantages of scaling the threshold voltage with supply voltage are emphasized.
Keywords :
integrated circuit technology; CMOS technology scaling; low voltage low power applications; optimum device structures; physically based models; power consumption reduction; scaling guidelines; supply voltage; threshold voltage; Analytical models; CMOS technology; Capacitors; Circuit simulation; Delay; Energy consumption; Guidelines; Low voltage; Semiconductor device modeling; Threshold voltage;
Conference_Titel :
Low Power Electronics, 1994. Digest of Technical Papers., IEEE Symposium
Conference_Location :
San Diego, CA, USA
Print_ISBN :
0-7803-1953-2
DOI :
10.1109/LPE.1994.573201
