Title :
Reducing transition counts in arithmetic circuits
Author :
Ercegovac, M.D. ; Lang, T.
Author_Institution :
Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
Abstract :
We present an approach to reducing the average number of signal transitions (T/sub /spl alpha//spl nu//) in the design of sign-detection and comparison of magnitudes. Our approach reduces Ta/sub /spl nu// from 21n/8 (n-operand precision in bits) to 8.5 in the case of iterative implementation, and from 5n to 5+n/8 in the tree network case. The approach is applicable to other arithmetic problems.
Keywords :
digital arithmetic; arithmetic circuits; iterative network; magnitude comparison; sign detection; signal transition counts; tree network; Circuits; Delay; Digital arithmetic; Iterative algorithms; Low power electronics;
Conference_Titel :
Low Power Electronics, 1994. Digest of Technical Papers., IEEE Symposium
Conference_Location :
San Diego, CA, USA
Print_ISBN :
0-7803-1953-2
DOI :
10.1109/LPE.1994.573205
