Title :
A 1-V low-power high-performance 32-bit conditional sum adder
Author :
Abu-Khater, I.S. ; Yan, R.H. ; Bellaouar, A. ; Elmasry, M.I.
Author_Institution :
AT&T Bell Labs., Holmdel, NJ, USA
Abstract :
A 32-bit conditional sum adder has been designed using a 0.5-/spl mu/m CMOS process with V/sub th/=0.2 V for 1-V operation. The simulated delay and power dissipation (at 30 MHz) are 9.8 ns and 310 /spl mu/W, respectively, as extracted from layout. The standby power is /spl sim/4 /spl mu/W. As a comparison, the same adder has a 5 ns delay, consuming 4.5 mW, if implemented on a standard 3V-process.
Keywords :
summing circuits; 0.5 micron; 1 V; 30 MHz; 310 muW; 32 bit; 9.8 ns; CMOS process; delay; layout; low-power conditional sum adder; power dissipation; simulation; standby power; Adders; CMOS process; Circuit simulation; Digital circuits; Energy consumption; Multiplexing; Power dissipation; Propagation delay; Signal design; Threshold voltage;
Conference_Titel :
Low Power Electronics, 1994. Digest of Technical Papers., IEEE Symposium
Conference_Location :
San Diego, CA, USA
Print_ISBN :
0-7803-1953-2
DOI :
10.1109/LPE.1994.573206
