Title :
A fully-static low power, high performance 64-bit 3-level carry skip adder
Author :
Turrini, S. ; Menon, S.
Author_Institution :
Western Res. Lab., Digital Equipment Corp., Palo Alto, CA, USA
Abstract :
We present in this paper a fully-static 8.1 ns 300 mW 64-bit adder, part of the integer data path of a complex CPU, designed for low power consumption, high-performance and using a today´s available 3.3 V 0.6 /spl mu/m CMOS process.
Keywords :
adders; 0.6 micron; 3.3 V; 300 mW; 64 bit; 8.1 ns; CMOS process; CPU; fully-static low power three-level carry skip adder; integer data path; Adders; CMOS logic circuits; CMOS process; CMOS technology; Circuit simulation; Delay; Energy consumption; Inverters; Logic design; Parasitic capacitance;
Conference_Titel :
Low Power Electronics, 1994. Digest of Technical Papers., IEEE Symposium
Conference_Location :
San Diego, CA, USA
Print_ISBN :
0-7803-1953-2
DOI :
10.1109/LPE.1994.573207
