Title :
Design considerations for low-power, high-speed CMOS analog/digital converters
Author :
Cho, T.B. ; Cline, D.W. ; Conroy, C.S.G. ; Gray, P.R.
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
Abstract :
This paper reviews architectural and circuit design considerations for realization of low power dissipation in high-speed CMOS A/D converters. Basic limitations on achievable power dissipation in MOS samplers and quantizers is first discussed. Then a number of practical design aspects are illustrated with discussion of a 10-bit, 20-Msample/s pipeline A/D converter implemented in 1.2-/spl mu/m CMOS technology which achieves a power dissipation of 35 mW at full speed operation on a 3.3 V power supply.
Keywords :
CMOS integrated circuits; 1.2 micron; 10 bit; 3.3 V; 35 mW; MOS quantizers; MOS samplers; architecture; circuit design; low-power high-speed CMOS analog/digital converters; pipeline A/D converter; power dissipation; Analog-digital conversion; Capacitors; Latches; Pipelines; Power dissipation; Quantization; Sampling methods; Signal to noise ratio; Uncertainty; Voltage;
Conference_Titel :
Low Power Electronics, 1994. Digest of Technical Papers., IEEE Symposium
Conference_Location :
San Diego, CA, USA
Print_ISBN :
0-7803-1953-2
DOI :
10.1109/LPE.1994.573208
