DocumentCode
2754548
Title
Novel design of priority arbiter
Author
Bahbouh, Hussein T. ; Khalil, Ahmed H. ; Salama, Aly E.
Author_Institution
Fac. of Eng., Cairo Univ., Egypt
fYear
1999
fDate
23-25 Feb 1999
Abstract
Many digital circuits with asynchronous inputs are susceptible to failure even when all their components are fault-free. They may fail as a result of metastable operation when their inputs have critical timing combinations. This paper addresses a novel priority arbiter architecture to solve the metastability problem. SPICE simulation is used to verify its performance and correctness. In contrast to other arbiters, the results showed that this new design has better immunity against metastable operation
Keywords
CMOS logic circuits; circuit simulation; circuit stability; integrated circuit reliability; synchronisation; SPICE simulation; asynchronous inputs; critical timing combinations; design; digital circuits; failure; metastable operation; performance; priority arbiter; Circuit simulation; Digital circuits; Flip-flops; Metastasis; SPICE; Strontium; Switches; Synchronization; Timing; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Radio Science Conference, 1999. NRSC '99. Proceedings of the Sixteenth National
Conference_Location
Cairo
Print_ISBN
977-5031-62-1
Type
conf
DOI
10.1109/NRSC.1999.760897
Filename
760897
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