Title :
A 2.5-V 16-Mb DRAM in 0.5-/spl mu/m CMOS technology
Author :
Ellis, W.F. ; Adler, E. ; Kalter, H.L.
Author_Institution :
IBM Microelectron. Div., Essex Junction, VT, USA
Abstract :
Low-voltage circuit techniques for high-density DRAMs, and the utilization of these techniques on a 16-Mb DRAM operating over the 2.5-V specification range, are presented. The P-type array is designed using full-V/sub cc/ bit line precharge for fast signal development and optimal sense latch sensitivity. Performance and power are further enhanced by using a digital secondary sense amplifier (DSSA). A worst-case module access of 55 ns is obtained from chips fabricated in 0.5-/spl mu/m CMOS technology.
Keywords :
cellular arrays; 0.5 micron; 16 Mbit; 2.5 V; 55 ns; CMOS technology; P-type array; bit line precharge; digital secondary sense amplifier; high-density DRAMs; latch sensitivity; low-voltage circuit techniques; signal development; worst-case module access; CMOS technology; Capacitance; Circuits; Decision support systems; Low voltage; Page description languages; Power dissipation; Random access memory; Signal design; Threshold voltage;
Conference_Titel :
Low Power Electronics, 1994. Digest of Technical Papers., IEEE Symposium
Conference_Location :
San Diego, CA, USA
Print_ISBN :
0-7803-1953-2
DOI :
10.1109/LPE.1994.573215
