Title :
Pulsed power supply CMOS-PPS CMOS
Author_Institution :
AT&T Bell Labs., Murray Hill, NJ, USA
Abstract :
Low power dissipation using conventional CMOS circuits can be achieved if the power supply lead is ramped repetitively between VDD and VSS. During the power-down edge, the state of the chip is stored on parasitic capacitances. This quasi-static CMOS circuit technique is called PPS (Pulsed Power Supply) CMOS and reduces the power dissipation over conventional 0.9 /spl mu/m p/sup +/ epi CMOS by 10 X.
Keywords :
CMOS integrated circuits; 0.9 micron; PPS CMOS; VDD; VSS; low power electronics; parasitic capacitances; power dissipation; pulsed power supply; quasi-static CMOS circuit; repetitive ramping; Diodes; Inverters; MOS devices; Power dissipation; Pulse circuits; Pulsed power supplies; Resistors; Switches; Variable structure systems; Voltage;
Conference_Titel :
Low Power Electronics, 1994. Digest of Technical Papers., IEEE Symposium
Conference_Location :
San Diego, CA, USA
Print_ISBN :
0-7803-1953-2
DOI :
10.1109/LPE.1994.573219
